1. Field of the Invention
The present invention relates to a semiconductor fabricating method. More particularly, the present invention relates to a method of fabricating a source-side-injection (SSI) programming flash memory cell.
2. Description of the Related Art
Nonvolatile memories are currently used in electronic devices to store structure data, program data and other data during repeated reading and writing operations. The field of the nonvolatile memories has recently focused on the electrically erasable programmable read only memory (EEPROM).
A conventional EEPROM comprises a stacked gate, which is used for storing charge, a floating gate and a controlling gate, which is used for controlling data storage. The floating gate is located between the controlling gate and the substrate without connecting any conductive line. The controlling gate connects to a word line. A source region and a drain region, which are on opposite sides of the stacked gate and in the substrate, connect to a bit line.
A flash memory is a type of EEPROM. Since the flash memory has a high programming speed, there is a great development potential of flash memory. During a reading, a writing, a programming, or a erasure operation of the conventional flash memory, electrons flow through a channel to the floating gate. However, a high voltage is required to drive the electrons flowing through the channel to the floating gate when performing the reading, the writing, the programming, or the erasure operation. Unfortunately, applying the high voltage easily leads to a punch-through problem. This, in turn, causes current to occur between a source region and a drain region. The occurrence of current between the source region and the drain region may further lead to power consumption.
The source-side-injection (SSI) programming flash memory cell is a type of flash memory cell. Because the SSI programming flash memory cell can be performed with a lowered drain voltage, the SSI programming flash memory cell effectively prevents the occurrence of the punch-through problem.
FIGS. 1A through 1C are schematic, cross-sectional views showing a conventional method of fabricating a SSI programming flash memory cell.
In FIG. 1A, a substrate 100 comprising a stacked gate 101 is provided. The stacked gate 101 comprises a tunneling oxide layer 102, a polysilicon floating gate 104, an oxide layer 106, and a polysilicon controlling gate 108. An ion implantation is performed. The substrate 100 is lightly doped with n-type ions (shown as Nxe2x88x92 in FIG. 1A). Lightly doped regions 112 and 114 are formed in the substrate 100 on opposite sides of the stacked gate 101.
In FIG. 1B, a mask layer 120 is formed on one side of the substrate 100 to cover the lightly doped region 114. An ion implantation step is performed. The substrate 100 exposed by the mask layer 120 is heavily doped with n-type ions (shown as N+ in
FIG. 1B). A drain region 116 is formed in the substrate 100 beside the stacked gate 101 and in the substrate 100.
In FIG. 1C, a spacer 110, such as a silicon oxide layer, is formed on a sidewall of the staked gate 101. An ion implantation step is performed with the spacer 110 and the stacked gate 101 serving as masks. The substrate 100 is heavily doped with n-type ions (shown as N+ in FIG. 1C). A source region 118, which is next to a lightly doped region 114a, is formed in the substrate 100.
In the conventional method of fabricating the SSI programming flash memory cell, the source region 118 and drain region 116 have to be formed separately. Therefore, it needs an additional photo-mask procedure, as described in FIG. 1B. The fabrication cost thus is increased.
The invention provides a method of fabricating a flash memory cell. A stacked gate is formed on a substrate. Lightly doped regions are formed in the substrate and on opposite sides of the stacked gate. A first spacer and a second spacer are formed on opposite sidewalls of the stacked gate. The first spacer and the second spacer cover a portion of the lightly doped regions. A drain region is formed in the substrate beside the first spacer. A source region is formed in the substrate in the substrate beside the second spacer. A tilt implantation step is performed to extend the drain region into a portion of the substrate under the spacer.
The invention provides a method of fabricating a flash memory cell. A stacked gate is formed on a substrate. A first spacer and a second spacer are formed on opposite sidewalls of the stacked gate. A drain region is formed in the substrate beside the first spacer. A source region is formed in the substrate beside the second spacer. A first tilt implantation is performed to extend the drain region into a portion of substrate under the first spacer. A second tilt implantation is formed to form a lightly doped region in the substrate under the second spacer.
The invention provides a method of fabricating a flash memory cell. A stacked gate is formed on a substrate. A first spacer and a second spacer are formed on opposite sidewalls of the stacked gate. A first tilt implantation is performed to form lightly doped regions in the substrate on opposite side of the stacked gate. Portions of the lightly doped regions are under the first spacer and the second spacer. A drain region is formed in the substrate beside the first spacer. A source region is formed in the substrate beside the second spacer. A second tilt implantation is performed to extend the drain region into a portion of substrate under the first spacer.
The present invention forms a SSI programming flash memory cell with a lightly doped source region. The lightly doped source region easily provides hot electrons. Thus, the amount of current is increased during the reading operation. Because the drain voltage is lowered in the present invention, the present invention prevents the occurrence of a punch-through problem. In comparison with the conventional method, which needs an additional photo-mask procedure, the invention forms an asymmetric source/drain region by tilt implantation. The fabrication process thus is simplified, and the fabrication cost can be further reduced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.